Silicon Software [e] - microEnable III

The "XXL" is the flagship of the microEnable III product line. Besides the standard features of microEnable III, the "XXL" version supports up to two BASE or one MEDIUM camera with CameraLink interface.

The extended capability of the FPGA enables complex image pre-processing in hardware. The standard delivery contains an advanced applet set with a constant feature of 12bit processing accuracy. Further hardware-based features are implemented in a very high algorithmic quality.

microEnable III-XXL is especially designed for applications with need of custom-specific features and modifications. It is also the ideal hardware platform in combination with VisualApplets®. VisualApplets® allows a user-specific programming of the FPGA processor of microEnable III-XXL.

The frame grabber system of microEnable III-XXL is extensible in different ways. In combination with the master-slave mode of the opto-coupled trigger board, several grabbers can be comfortably synchronized and controlled. By use of CameraLink duplicator CLIO, image data can be distributed and processed on up to 256 microEnable III-XXL boards.

microEnable III-XXL is a highly programmable frame grabber with extended features and perfectly predetermined for a collaboration with VisualApplets®.

Applications with colour requirements means an operation with a high bandwidth of image data as well as a computationally expensive image processing.

A special applet on microEnable III-XXL is used for a conversion from Bayer pattern to RGB image data. The conversion from RGB to HSI colour space enables an easy definition of colour fields. These color fields can be defined by settings for limits and ranges for hue, saturation and intensity. The result of the segmentation is reconverted to RGB colour space. The complete process take place in real-time.

microEnable III-XXL uses complex algorithms for the Bayer pattern reconstruction to RGB colours. With a 7*7 Laplacian method, the output of the image data is very close to the quality of 3-chips cameras. Tremendous approvements are achieved especially in the display of edges and the calculation of homogenous colour areas.

microEnable III-XXL is delivered with software version 3.1, which includes advanced applets for high quality image processing with no compromises to the performance. Especially the constant feature of 12bit processing, the implementation of the knee lookup table for image quality enhancement and quality pre-processing for colour reconstruction and shading correction are the highlights of the new features.

Image data are internally processed with an accuracy of 12bit, without loss of performance. To save the high bit-depth quality, the output of the image data is in 16bit. Even Bayer recalculation and shading correction is processed in 12bit.

The 12XXL applets allow an image size of up to 16k widths by 64k heights. Only Bayer colour applets and Shading applets are limited to 2k (7*7 Bayer HQ) widths, 4k (3*3 Dual Bayer) widths and 4k by 4k area size (2D Shading).

The Knee Lookup table is a mighty tool for enhancements of the image quality or the calibration of the camera. It internally works with an accuracy of 12bit input and 16bit output. Non-linear pixel modifications can be defined by 256 control points. The Knee Lookup table controls comfortably pre-settings for brightness, contrast and gamma.

The white balancing controls manually or automatically the configuration of the colour channels. The complete colour spectrum is used for a non-linear white balancing. Blue, Red and Green can be independently and separately configured.

The sensor readout correction allows the tap sorting of standard as well as non-standard cameras.

Line applets support shaft encoder (glass scale) functionality. A-B direction recognition is also supported as a compression of lines in rewind mode.

The serial RGB output is a special mode of some BASE line cameras. It enables a serial output of colour image data with a bit depth of more than 24bit.

Colour field array (CFA) cameras are greyscale cameras with a colour pattern coating. The original colour can be reconstructed by different algorithmic strategies. The 7*7 Bayer HQ methods is a computationally expensive processing with a high quality color output. The advantage of the 3*3 Bayer applets is the synchronous operation of two color cameras at the same time.

The spatial offset correction allows a compensation of static sensor noise by a subtractive shading correction.

The spatial scaling correction allows the compensation of static lightning effect by a multiplicative shading correction.

The defect pixel interpolation allows the content-based completion of an image for static white and black pixels by an interpolation of the surrounding pixels. White and black pixels arise by powerless or always powered CMOS sensor units.

1) High quality Bayer pattern reconstruction by 7*7 Laplace interpolation method; 2) Bayer pattern reconstruction by 3*3 bilinear interpolation method

microEnable III and microEnable III-XXL are 64 bits/66 MHz frame grabber cards which stand out due to highest performance and efficiency. The modern PCI-64 bus enables a four times higher data transfer between PCI-periphery and mainboard. microEnable III product line prevents data transfer bottlenecks by this technology, however, remains compatible to PCI 32 standard computers.

Constant data transfer rates of over 200 MByte also guarantee the use of current high speed cameras. microEnable III is therefore suitable ideally as solution for time-critical tasks, particularly at the use of two cameras or for the acquiring of image sequences with a very high frame rate or very high resolution. Its onboard memory of 96 MByte SDRAM enables an acquiring of images without dropped frames. microEnable III is optimized for the two camera mode and the real time image pre-processing.

The integrated image pre-processing enables the relief of the main processor and guarantee a real.time ability in the execution of applications at the same time. As intelligent frame grabber it enables an efficient adaptation to new applications and camera specifications by additional programming of its integrated processor.

Why the specialization on CameraLink?
The CameraLink technology offers the combination from highest efficiency and simple system integration. The specification enables a data transfer of up to 250 MByte/sec. over one single cable. At two cables even till almost 700 MByte/sec. It is therefore the ideal interface for high speed cameras of the today's and the next generation.
Besides the image data both the camera trigger and the configuration are transferred on a standardized cable. One single cable suffices. This is moreover also extremely flexible because of the serial transmitting. Together with the standardized software interface CameraLink enables a simple and elegant integration into your application.
The microEnable frame grabber allows the operation of CameraLink cameras in BASE mode (1 cable up to 250 MByte/sec.) or MEDIUM mode (2 cables up to 500 MByte/sec.). The synchronous operation of two cameras are also able in addition.

The microEnable III frame grabber uses the coprocessor of the Xilinx Spartan2 FPGA series, owns two CameraLink connectors, a trigger hardware connector and a further hardware connector for optional signal inputs and outputs.

Technical description
Data sheets		language
	microEnable III data sheet	ger/en	Description of microEnable III (ger/en) exclusively
	microEnable product line data sheet	ger/en	Description of product line microEnable I to microEnable III (ger/en)

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Product line
Product models		Additional interfaces
	microEnable III MXC2S-300 microEnable with Xilinx Spartan XC2S-300 coprocessor		Trigger interface with 4 TTL inputs and 8 TTL outputs
	microEnable III-XXL MXC2S-600 microEnable with Xilinx Spartan XC2S-600 coprocessor		OPTO-Trigger interface with 4 TTL inputs and 8 TTL outputs (opto couppled)
			CLIO (CameraLink Input Output Unit) for distribution of the camera data to up t 256 microEnable III boards

comparison table microEnable III / microEnable III-XXL
	standard version	XXL-version
Vision processor
Xilinx FPGA	Spartan XC2S 300 E	Spartan XC2S 600 E
Pre-processing capability	high	very high
Hardwareausstattung
PC interface	PCI 64-bit/66MHz
On-board memory	96 MBytes
Camera interface	2 CameraLink inputs
Digital interface	Trigger interface, digital I/O
Hardware applets for Area Cameras
BASE configuration	Single Gray	Single Gray
	SingleBayer	SingleBayer
	Single RGB*	Single RGB
	Dual Gray	Dual Gray
	Dual RGB*	Dual RGB
	n/a	Dual Bayer
MEDIUM configuration	n/a	Area Gray
	n/a	Area RGB
Hardware applets for Line Cameras
BASE configuration	Single Gray	Single Gray
	Single RGB	Single RGB
	Dual Gray	Dual Gray
	Dual RGB	Dual RGB
MEDIUM configuration	n/a	Line Gray
	n/a	Line RGB

* in preparation

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System requirements
Supported operational systems (OS)		Camera compatibilities (selection)
	Windows XP		CameraLink compatible BASE cameras
	Windows Vista		CameraLink compatible MEDIUM cameras (supported by XXL version)
	Linux (up to kernel version 2.4.20 / 2.4.21) Please ask for your actual Kernel support.		Area- and line scan cameras
			Greyscale- and color cameras (Bayer filter, RGB)
			Single and Dual operation mode
			Please ask for your individual system configuration.

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