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microEnable II - the performance frame grabber
microEnable II is a frame grabber and processor board which stands out due to high performance and efficiency of its FPGA coprocessor. It is not only suitable as solution for time-critical tasks of sequence acquiring but also for image pre-processing in real time and complex data processing tasks, i.e for data compressing or encoding.
microEnable II is suitable for the acquiring of image sequences with a very high frame rates or very high resolution. Its optional memory upgrading to 512 MByte SDRAM (availability of 10/2002) enables sufficient resources for acquiring of images withour dropped frames. microEnable II is optimized particularly for the two camera mode and the real time image pre-processing. As intelligent frame grabber it enables an efficient adaptation to new applicatons and camera specifications by additional programming of its integrated processor.
The microEnable II frame grabber uses the coprocessor of the Xilinx Virtex FPGA series and enables modular extensions with the CMC hardware connections by IEEE specification P1386 (common mezzanine cards).

| Technical features |
| General features |
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Hardware features |
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Exploitation of the complete physical memory |
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Xilinx Virtex XCV1000-4 FPGA with 2 * 512 KB fast SRAM memory |
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Multiprocessor-capability |
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PCI 32-bit /33 MHz interface |
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Multi PCI-bus capability (only limited by numbers of available PCI-busses) |
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optional memory upgrade up to 512 MB SDRAM |
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Programming of individual solutions by direct access to FPGA-coprocessor |
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2 x DMA channels |
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| Pre-processing features |
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Camera features |
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Image preprocessing applets included (please ask for compatibility) |
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Simultaneous run of two cameras in dual operation mode |
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I.e. Bayer correction, shading correction and spatial correction |
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Independent operation and control of cameras |
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Special feature: additional image preprocessing on demand |
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Asynchronous image recording in triggered mode |
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Seperated framebuffers |
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| Software features |
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Performance data |
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Software development kit (SDK) for programming interfaces between microEnable and your application |
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Camera frequency up to 66 MHz clock rate |
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Diagnostic tools for a quick and uncomplicated overview of operational functionality and benchmarking of the system |
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Area cameras up to 4K*4K pixels |
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microDisplay for previewing and acquiring of camera sequences |
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Line cameras up to 16K pixels |
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microDisplay for con trolling of the camera parameters and trigger settings |
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Over 100 MByte/s continous datatransfer rate to user-memory |
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CHDL-library with basic applets for imagery functions and basis for programming individual applets |
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Framerate up to 10.000 f/s |
| Technical description |
| Data sheets |
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microEnable II data sheet |
ger/en |
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Description of microEnable II (ger/en) exclusively |
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microEnable product line data sheet |
ger/en |
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Description of product line microEnable I to microEnable III (ger/en) |
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| Documents |
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Manuals |
ger/en |
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| Product line |
| Product models |
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Additional interfaces |
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MV1000 microEnable with Xilinx Virtex XCV1000-4 FPGA and 2 * 512 KB SRAM memory |
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Interface for up to 2 CameraLink/Channel-Link cameras |
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Interface for up to 2 LVDS/RS644 cameras |
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Interface for up to 2 RS422 cameras |
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Trigger interface with 4 TTL inputs and 4 TTL outputs |
| System requirements |
| Supported operational systems (OS) |
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Camera compatibilities (selection) |
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Windows NT Version 4.0 |
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Basler
A101, A101c, A101p, A101cp, A113 , A113c, A201b, A201bc, A202k, A301b, A301bc, A302b, A302bc, A501k, L101-1k, L101-2k, L101b-1k, L101b-2k, L101k-1k, L101k-2k, L103-1k, L103-2k, L104-1k, L104-2k, L201, L203, L301bc, L320c |
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Windows 2000 Professional |
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Pulnix
TM-6710, TM-9701, TM-1001, TM-1010, TM-1020-15, TM-1020-30, TM-1040, TM-1300, TMC-6700, TMC-1000 |
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Windows XP (beta) |
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PhotonFocus
MV-D1024k-28CL, MV-D1024k-28CL10, MV-D1024k-80CL |
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Linux (up to kernel 2.4.10) |
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Please ask for your individual system configuration |
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